Presentation
Design Validation Engineering Intern
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d-Matrix Corporation
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Santa Clara, Ca
SessionJob Postings
DescriptionThe role: Design Validation Engineering Intern
What You Will Do:
- Development of tools and methodologies for silicon validation:
- Automation of data collection
-Instrument control interface
- Database back end including outlier detection and classification
- Data post processing and analysis for margining and debug
- Linear and logical regression, clustering, plot and report generation
- Work with high speed serial interfaces including PCI Express Gen5, LPDDR5 memory, and die to die interconnections on multi-chip module
What You Will Do:
- Development of tools and methodologies for silicon validation:
- Automation of data collection
-Instrument control interface
- Database back end including outlier detection and classification
- Data post processing and analysis for margining and debug
- Linear and logical regression, clustering, plot and report generation
- Work with high speed serial interfaces including PCI Express Gen5, LPDDR5 memory, and die to die interconnections on multi-chip module
RequirementsWhat you will bring:
- Familiarity with hardware systems, advanced electronic circuits, signals and systems
- Lab coursework and/or experience
- Solid knowledge and understanding of probability and statistical science
- Strong C and Python programming skills
- Excellent verbal and written communication skills
- Attending graduating year of graduate school program
Company Descriptiond-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.
Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.
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Event Type
Job Posting
TimeTuesday, 19 November 202410:30am - 3pm EST
LocationExhibit Hall A3 - Job Fair Inside
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