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Lowering the Barriers to Programming FPGAs and AIEs for HPC
DescriptionWe have seen great advances in the hardware and software ecosystem for FPGAs in recent years, with the release of ever more powerful FPGAs with specialised hardened components such as AI Engines for accelerating compute, and large investment put into tooling, high level synthesis and libraries. However there is still a disconnect between HPC developers, many of whom still write their codes in Fortran, and effectively run codes on these architectures, currently requiring the redevelopment of codes that involves significant time and expertise. In this talk I will describe our work leveraging MLIR to identify and seamlessly offload key computational components of programmer's a code to FPGAs and AIEs based upon the underlying algorithmic pattern. With the objective of requiring no code-level modifications to be made by the programmer, our approach connects frontends such as Flang to AMD's MLIR-AIE dialects and HLS LLVM backend to deliver optimised execution on FPGAs and AIEs.
Event Type
Workshop
TimeFriday, 22 November 20249:20am - 9:40am EST
LocationB208
Tags
Embedded and/or Reconfigurable Systems
Heterogeneous Computing
Registration Categories
W