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A Co-Design Approach to NUMA Architectures in HPC: Quantitative Evaluation and Design Exploration
DescriptionUnderstanding the performance potential and data placement challenges in Non-Uniform Memory Access (NUMA) architectures is crucial for optimizing High-Performance Computing (HPC) systems. We will present a quantitative approach, using simulations and models, that provides essential insights into how system architecture impacts microbenchmarks and real-world applications. We model a NUMA architecture with ARMv8 Neoverse V1 processors, leveraging the gem5 and VPSim simulation platforms. Combining these tools enables us to optimize simulation speed during early-stage exploration while preserving the accuracy necessary to evaluate design performance in later stages.We will present case studies that examine the performance implications of different NUMA node configurations, SLC (System Level Cache) group assignments, and Network-on-Chip (NoC) settings. These case studies reveal critical design trade-offs, offering valuable input for the co-design process, where HPC SoC architects and system integrators collaborate. This work is conducted within the European Processor Initiative (EPI) framework, focusing on developing new, energy-efficient hardware architectures for future exascale systems.
