Presentation
Software-Hardware Codesign Lessons Learned from the IARPA AGILE FORZA Project
DescriptionIn this talk, we introduce a new programming system for Partitioned Global Address Space (PGAS) applications, where point-to-point remote operations can be expressed as fine-grained asynchronous active messages (or equivalently, as remote asynchronous tasks). One of the major benefits of this approach is that it enables asynchronous movement of computation to data as opposed to traditional approaches of more synchronous movement of data to computation. This approach can be viewed as extending the classical Bulk Synchronous Processing (BSP) model to a Fine-grained-Asynchronous Bulk-Synchronous Parallelism (FA-BSP) model. We will discuss an actor-based programming system to realize the FA-BSP execution model, and present recent results illustrating the benefits of this approach on current HPC systems.
Looking to the future, we will also discuss ongoing work on hardware support of the FA-BSP execution model being undertaken in the Flow-Optimized Reconfigurable Zones of Acceleration (FORZA) project led by Georgia Tech that is supported by the IARPA AGILE program. The FORZA project is pursuing a software-hardware co-design approach to address the significant disruptions currently under way in HPC hardware and software. In hardware, there is a Pandora's box of new architectural approaches being proposed to sustain performance improvements beyond the end of Moore’s Law. In software, there is an increased urgency for enabling large-scale data analytics applications for societal benefits. To address these challenges, the FORZA project is focusing on large-scale graph analytics as an important exemplar of the challenges that need to be addressed by future HPC systems.
We would like to acknowledge all participants in the FORZA project from Georgia Tech, Cornelis Networks, Tactical Computing Labs, UC Santa Barbara, and U. Notre Dame. The opinions in this talk are solely those of the speaker and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of any of these organizations, the ODNI, IARPA, or U.S. Government.
Looking to the future, we will also discuss ongoing work on hardware support of the FA-BSP execution model being undertaken in the Flow-Optimized Reconfigurable Zones of Acceleration (FORZA) project led by Georgia Tech that is supported by the IARPA AGILE program. The FORZA project is pursuing a software-hardware co-design approach to address the significant disruptions currently under way in HPC hardware and software. In hardware, there is a Pandora's box of new architectural approaches being proposed to sustain performance improvements beyond the end of Moore’s Law. In software, there is an increased urgency for enabling large-scale data analytics applications for societal benefits. To address these challenges, the FORZA project is focusing on large-scale graph analytics as an important exemplar of the challenges that need to be addressed by future HPC systems.
We would like to acknowledge all participants in the FORZA project from Georgia Tech, Cornelis Networks, Tactical Computing Labs, UC Santa Barbara, and U. Notre Dame. The opinions in this talk are solely those of the speaker and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of any of these organizations, the ODNI, IARPA, or U.S. Government.
