Presentation
European RISC-V based accelerators for HPC - overview and roadmap
DescriptionThe STX and VEC accelerators being developed by the European Processor Initiative (EPI) are targeting the HPC market with different approaches. The STX is co-designed for algorithms that prevail in hpc simulation applications. It's tuned using features from previous architectures like BlueGene, IBM Cell and GPUs, and leverages current Open Source developments on hardware and software. In order to easily utilize the computational units, it implements novel multi-hierarchy offloading features added to OpenMP and automatic DMA instruction injection via LLVM optimization passes. STX is not only a chip - but a full system approach. A company called UNEEC Systems was founded for sales and the development of the next generations of STX systems.
VEC is a highly efficient vector processor positioned as a general purpose HPC accelerator. Using RISC-V vector extensions and cache coherence, even legacy codes are easily ported to this accelerator through its self-booting capability. Additionally, VEC is power- and area-efficient through its use of single-ported register file design and simple ring-based inter-lane connect while featuring the longest vector length (up to 2048 Double Precision FP elements) of any Vector Processor.
This talk will give a brief overview over the concepts behind the two accelerator developments and presents a roadmap.
VEC is a highly efficient vector processor positioned as a general purpose HPC accelerator. Using RISC-V vector extensions and cache coherence, even legacy codes are easily ported to this accelerator through its self-booting capability. Additionally, VEC is power- and area-efficient through its use of single-ported register file design and simple ring-based inter-lane connect while featuring the longest vector length (up to 2048 Double Precision FP elements) of any Vector Processor.
This talk will give a brief overview over the concepts behind the two accelerator developments and presents a roadmap.