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RISC-V and HPC: How Can We Benefit from the Open Hardware Revolution?
DescriptionRISC-V is an open standard Instruction Set Architecture (ISA) which enables the open development of CPUs and a shared common software ecosystem. With over 15 billion RISC-V cores, which is accelerating rapidly, we are seeing a revolution driven by open hardware. Nonetheless, for all the successes that RISC-V has faced, it is yet to become popular in HPC. Recent advances, however, such as the vectorisation standard and data centre RISC-V hardware, make this technology a more realistic proposition for our workloads.

This panel brings together a range of experts in RISC-V with the HPC community to explore the advantages, challenges, and opportunities that the openness of RISC-V can bring to HPC, as well as opportunities for us to mould RISC-V to suit our needs. Led by the RISC-V HPC SIG, interested attendees can then join us and participate in one of the most exciting open-source technological activities of our time.