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Scalable Low-Latency Hardware Function Chaining with Chain Control Circuit
DescriptionTo deliver advanced services with high performance and flexibility, we are developing a computing platform that integrates various hardware accelerators (HWAs). Our goal is to build customized services for each user by combining application functions. To achieve this, we propose Hardware Function Chaining (HFC) technology that enables sharing a stateful function among multiple users and low-latency data transfer between HWAs. HFC uses a chain control circuit that allows the HWA to autonomously manage the destinations of multiple data flows (function chains). This method avoids CPU bottlenecks. We compared our HFC-based system with a look-aside configuration, where chain control is handled by the CPU, and evaluated the performance involving up to eight NOP functions in scenarios with multiple different function chains. The results showed that our approach reduces latency to up to 1/13 that of the look-aside configuration and maintains a stable latency and throughput as the system scales.
Event Type
ACM Student Research Competition: Graduate Poster
ACM Student Research Competition: Undergraduate Poster
Doctoral Showcase
Posters
TimeTuesday, 19 November 202412pm - 5pm EST
LocationB302-B305
Registration Categories
TP
XO/EX