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Web-Based Simulator of Superscalar RISC-V Processors
SessionInternational Workshop on RISC-V for HPC (RISCVHPC)
DescriptionMastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar processors and HW/SW co-design. With customizable processor architecture, full C compiler support, and detailed performance statistics, this tool offers a comprehensive learning experience.
Author/Presenters
Jiri Jaros
Brno University of Technology
Faculty of Information Technology
Michal Majer
Brno University of Technology
Faculty of Information Technology
Jakub Horky
Brno University of Technology
Faculty of Information Technology
Jan Vavra
Brno University of Technology
Faculty of Information Technology
Event Type
Workshop
TimeMonday, 18 November 20244:30pm - 4:50pm EST
LocationB315
Tags
Accelerators
Emerging Technologies
Hardware Technologies
Registration Categories
W
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