Presenter

Dr. Daniele Cesarini is a project manager and HPC technology specialist in the HPC department of CINECA, where his work is focused on the design of the next-generation HPC architectures to define the strategic roadmap of Italian and European supercomputers. He is Vice Chair for Research of ETP4HPC and he serves on the scientific advisory board of EuroHPC JU (RIAG). He manages for CINECA several European-founded projects (EPI-SGA1, EPI-SGA2, EUPEX, REGALE, etc.) and national projects of the Italian Recovery and Resilience Plan (PNRR). He graduated in computer engineering from the University of Bologna (Italy) in 2014, where he also earned his PhD in electronics, telecommunications, and information technologies engineering in 2019.