Presenter
Teresa Cervero Garcia

Biography
Teresa Cervero Garcia is a leading research engineer at Barcelona Supercomputing Center (BSC), working on the MareNostrum Experimental Exascale Platform (MEEP) project, which is a flexible FPGA-based emulation platform that explores hardware/software co-designs for exascale supercomputers and other hardware targets, based on European-developed IP. A major part of this has been to define, develop, and deploy an FPGA-based emulation platform targeting European-based exascale supercomputer RISC-V-based IP development, which Dr. Cervero is heavily involved in. She is also vice-chair of the RISC-V HPC SIG. She earned her PhD in telecommunication engineering, focusing on hardware design with experience on HDL languages and FPGA devices.
Presentations
Panel
Architecture
Hardware Technologies
TP
Chair of Sessions
Workshop
Accelerators
Emerging Technologies
Hardware Technologies
W
Committee Roles
SC Workshop Organizer: RISC-V
SC Workshop Committee Member: RISC-V