Presenter

Dr. Jeffrey Young is a research scientist with Georgia Tech’s Partnership for Advanced Computing Environments (PACE). In collaboration with other GT faculty, Dr. Young has led the initial development of the Rogues Gallery, an NSF-funded testbed focused on novel hardware that might be considered rogue by today’s standards but that may be critical for performance in future HPC systems. The Rogues Gallery currently hosts an Emu Chick prototype, SmartNICs, novel FPGA and 3D stacked memory devices, power monitoring equipment, and the Field Programmable Analog Array, a low-power device that can be used to implement neuromorphic algorithms. In addition to testbed-related work, Dr. Young’s other research interests include the development of interconnects, accelerators, and memory abstractions to support high-performance applications and algorithms.