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Workshop: Fourth International Symposium on Quantitative Codesign of Supercomputers
DescriptionThis symposium considers combining two methodologies—collaborative codesign and data-driven analysis—to realize the potential of supercomputing more fully. The rapidly evolving nature of HPC and its importance to scientific discovery make it an excellent candidate for both codesign processes and data-driven approaches. Today’s HPC centers store vast sums of information, yet using this data presents demanding challenges. Much of the data-driven challenge has to do with discovering, accessing, and analyzing the right data. Codesign also presents formidable challenges. For example, how can a codesign development use the data collected on current systems to facilitate the design of next-generation supercomputers and successfully support our upcoming environments. Quantitative codesign offers a collaborative evidence-based approach to address our existing needs and our upcoming ambitions. This symposium will bring together leaders in the field to review current efforts across centers and discuss areas that show potential.

This year, our theme is on opportunities and challenges in ADVANCED MEMORY. There are new research topics in heterogeneous computing, energy efficient computing performance, AI architectures, and edge computing that are driving innovations in advanced memory technology. Generative AI, Foundation Models, and HPC are important drivers for performance improvements in high bandwidth memory. Growing industry support and adoption of Compute Express Link (CXL) is driving interesting codesign explorations with various application drivers for CXL capabilities including: multi-tiered memory hierarchy, memory disaggregation large memory pools with global fabric attached memory, support for heterogeneous computing with shared memory pools, and revisited concepts for compute near memory designs. In shared memory, application codesign tradeoffs are raised for hardware vs software coherency and consistency management. New codesign opportunities also arise to understand memory requirements for Federated Learning at low power edge devices.
Event TypeWorkshop
TimeSunday, 17 November 20249am - 12:30pm EST
LocationB304
Tags
Codesign
Data Movement and Memory
Facilities
Registration Categories
W