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Workshop: Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures
DescriptionNext-generation HPC platforms deal with increasing heterogeneity in their subsystems. These subsystems include internal high-speed fabrics for inter-node communication; storage system integrated with programmable data processing units (DPUs) and infrastructure processing units (IPUs) to support software-defined networks; traditional storage infrastructures with global parallel POSIX-based filesystems complemented with scalable object stores; and heterogeneous compute nodes configured with a diverse spectrum of CPUs and accelerators (e.g., GPU, FPGA, AI processors) having complex intra-node communication. The workshop will pursue multiple objectives, including: (1) develop and provide a holistic overview of next-generation platforms with an emphasis on communication, I/O, and storage at scale, (2) showcase application-driven performance analysis with various HPC network fabrics, (3) present experiences with emerging storage concepts like object stores and all-flash storage, (4) share experiences with performance tuning on heterogeneous platforms from multiple vendors, and (5) share best practices for application programming with complex communication, I/O, and storage at scale.
Presentations
9:00am - 9:05am ESTIXPUG: Introduction and Welcome
Presenter
9:05am - 10:00am ESTFrom Tensor Processing Primitive towards Tensor Compilers using upstream MLIR
10:00am - 10:30am ESTIXPUG : Morning Break
10:30am - 11:00am ESTCan Current SDS Controllers Scale To Modern HPC Infrastructures?
11:00am - 11:30am ESTBenchmarking Ethernet Interconnect for HPC/AI workloads
11:30am - 12:00pm ESTPredicting Protein Folding on Intel’s Data Center GPU Max Series Architecture (PVC)
12:00pm - 12:30pm ESTAn Efficient Checkpointing System for Large Machine Learning Model Training
12:30pm - 2:00pm ESTIXPUG : Lunch
2:00pm - 3:00pm ESTKeynote : Network and Communication Infrastructure powering Meta’s GenAI and Recommendation Systems
3:00pm - 3:30pm ESTIXPUG : Afternoon Break
3:30pm - 4:00pm ESTProtocol Buffer Deserialization DPU Offloading in the RPC Datapath
4:00pm - 4:30pm ESTModeling and Simulation of Collective Algorithms on HPC Network Topologies using Structural Simulation Toolkit
Author/Presenter
4:30pm - 5:00pm ESTPerformance analysis of a stencil code in modern C++
5:00pm - 5:30pm ESTIXPUG : Open Discussion and Wrapup
Presenter