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DTSTART;TZID=America/New_York:20241117T083000
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UID:submissions.supercomputing.org_SC24_sess409_tut133@linklings.com
SUMMARY:Leveraging SmartNICs for HPC Applications
DESCRIPTION:Jeffrey Young (Georgia Institute of Technology), Richard Graha
 m (NVIDIA Corporation), Oscar Hernandez (Oak Ridge National Laboratory (OR
 NL)), Antonio Peña (Barcelona Supercomputing Center (BSC)), Richard Vuduc 
 (Georgia Institute of Technology), and Clay Hughes (Sandia National Labora
 tories)\n\nThe past few years have witnessed an increased support for prog
 rammable network adapters, known as “Smart-NICs", that offer additional fu
 nctionalities beyond standard packet processing capabilities. These device
 s often feature programmable lightweight processing cores, FPGAs, and even
  CPU- and GPU-based platforms capable of running separate operating system
 s. Their primary target has been data center operations, such as infrastru
 cture management, packet filtering, and I/O acceleration, but are increasi
 ngly being explored for high-performance\ncomputing (HPC) application acce
 leration.\n\nThis tutorial offers an in-depth exploration of the state-of-
 the-art for SmartNICs and the emerging software ecosystems supporting them
 . Attendees will engage in hands-on exercises to better understand how to 
 take advantage of SmartNICs for application acceleration, including MPI co
 llective operation offloading, OpenMP offload, system security, file I/O, 
 and algorithmic modifications to maximize on-board processing power. Parti
 cipants will have the opportunity to execute these exercises using cutting
 -edge SmartNICs like NVIDIA’s BlueField-3 Data\nProcessing Unit (DPU). The
  tutorial presenters will discuss additional techniques for optimizing app
 lications to harness SmartNICs as communication accelerators in HPC system
 s.\n\nTag: Accelerators, Architecture, Emerging Technologies, Network\n\nR
 egistration Category: Tutorial Reg Pass\n\n
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