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DTSTAMP:20260422T143138Z
LOCATION:B211
DTSTART;TZID=America/New_York:20241118T083000
DTEND;TZID=America/New_York:20241118T170000
UID:submissions.supercomputing.org_SC24_sess430_tut179@linklings.com
SUMMARY:High-Performance and Smart Networking Technologies for HPC and AI
DESCRIPTION:Dhabaleswar Panda, Hari Subramoni, Benjamin Michalowicz, Chen-
 Chun Chen, and Nick Contini (The Ohio State University)\n\nHigh-Performanc
 e Networking technologies are generating a\nlot of excitement towards buil
 ding next-generation High-End\nComputing (HEC) systems for HPC and AI with
  GPGPUs,\naccelerators, and Data Center Processing Units (DPUs), and a\nva
 riety of application workloads. This tutorial will provide\nan overview of
  these emerging technologies, their\narchitectural features, current marke
 t standing, and\nsuitability for designing HEC systems. It will start with
  a\nbrief overview of IB, HSE, RoCE, and Omni-Path interconnect.\nAn in-de
 pth overview of the architectural features of these\ninterconnects will be
  presented with associated hands-on\nexercises. It will be followed with a
 n overview of the\nemerging NVLink, NVSwitch, EFA, and Slingshot\narchitec
 tures. We will then present advanced features of\ncommodity high-performan
 ce networks that enable performance\nand scalability. We will then provide
  an overview of\nenhanced offload capable network adapters like DPUs/IPUs\
 n(Smart NICs), their capabilities and features.  Next, an\noverview of sof
 tware stacks for high-performance networks\nlike Open Fabrics Verbs, LibFa
 brics, and UCX comparing the\nperformance of these stacks will be given. N
 ext, challenges\nin designing MPI library for these interconnects, solutio
 ns\nand sample performance numbers will be presented. Finally,\nwe will ha
 ve a set of additional hands-on sessions to understand \nperformance of ne
 tworking technologies.\n\nTag: Parallel Programming Methods, Models, Langu
 ages and Environments\n\nRegistration Category: Tutorial Reg Pass\n\n
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