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DTSTAMP:20250626T234541Z
LOCATION:B302-B305
DTSTART;TZID=America/New_York:20241119T120000
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UID:submissions.supercomputing.org_SC24_sess487_post122@linklings.com
SUMMARY:Scalable Low-Latency Hardware Function Chaining with Chain Control
  Circuit
DESCRIPTION:Yuta Ukon, Takahiro Kawahara, Yuki Arikawa, Naoki Miura, and T
 eruaki Ishizaki (NTT Corporation); Wataru Kanemori, Ryoko Tamura, and Kenj
 iro Mori (Fujitsu Ltd); and Takeshi Sakamoto (NTT Corporation)\n\nTo deliv
 er advanced services with high performance and flexibility, we are develop
 ing a computing platform that integrates various hardware accelerators (HW
 As). Our goal is to build customized services for each user by combining a
 pplication functions. To achieve this, we propose Hardware Function Chaini
 ng (HFC) technology that enables sharing a stateful function among multipl
 e users and low-latency data transfer between HWAs. HFC uses a chain contr
 ol circuit that allows the HWA to autonomously manage the destinations of 
 multiple data flows (function chains). This method avoids CPU bottlenecks.
  We compared our HFC-based system with a look-aside configuration, where c
 hain control is handled by the CPU, and evaluated the performance involvin
 g up to eight NOP functions in scenarios with multiple different function 
 chains. The results showed that our approach reduces latency to up to 1/13
  that of the look-aside configuration and maintains a stable latency and t
 hroughput as the system scales.\n\nRegistration Category: Tech Program Reg
  Pass, Exhibits Reg Pass\n\nSession Chairs: Ayesha Afzal (Friedrich-Alexan
 der University, Erlangen-Nuremberg; Erlangen National High Performance Com
 puting Center); Sally Ellingson (University of Kentucky); and Alan Sussman
  (University of Maryland)\n\n
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