BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/New_York
X-LIC-LOCATION:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260924T172456Z
LOCATION:B206
DTSTART;TZID=America/New_York:20241121T113000
DTEND;TZID=America/New_York:20241121T120000
UID:submissions.supercomputing.org_SC24_sess698_exforum163@linklings.com
SUMMARY:Exploring CXL 3.1-Enabled Composable Servers: Building Blocks for 
 Next-Generation HPC Systems
DESCRIPTION:Yongjin Cho (Panmnesia)\n\nCompute express link (CXL) is gaini
 ng attention as a practical solution that can reduce total cost of ownersh
 ip (TCO) of HPC and datacenters while providing reasonable performance. In
  this presentation, we will introduce how to utilize the recent version of
  CXL technology, CXL 3.1, to construct a composable HPC server and how the
  CXL 3.1-enabled composable server can accelerate practical HPC applicatio
 ns.\n\nThe composable server consists of CPU and memory nodes. Since each 
 node features a CXL 3.1 switch that supports multi-level switching and por
 t-based routing, it can connect multiple nodes with flexibility. Using thi
 s composable server, we will demonstrate the effectiveness of CXL 3.1 tech
 nology. To this end, we will show a demo running practical HPC application
 s (e.g., atomic-level simulation) on the CXL 3.1 composable server. Our de
 mo shows that the CXL-based server outperforms the conventional system by 
 about 1.8 times, through the utilization of memory sharing features.\n\nTa
 g: Hardware Technologies\n\nRegistration Category: Tech Program Reg Pass, 
 Exhibits Reg Pass\n\nSession Chair: Jane Herriman (Lawrence Livermore Nati
 onal Laboratory (LLNL))\n\n
END:VEVENT
END:VCALENDAR