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UID:submissions.supercomputing.org_SC24_sess748_ws_pmbsf104@linklings.com
SUMMARY:Performance Analysis of Runtime Handling of Zero-Copy for OpenMP P
 rograms on MI300A APUs
DESCRIPTION:Carlo Bertolli (AMD, Inc.) and Thorsten Blass, Jan-Patrick Leh
 r, Doru Bercea, Dhruva Chakrabarti, Lynd Stringer, Nicole Aschenbrenner, L
 awrence Meadows, and Ron Lieberman (AMD Research)\n\nIn current discrete G
 PU systems, the penalty of data movement between host and device memory is
  inevitable, forcing many large-scale applications to include optimization
 s that amortize this cost. On systems like the AMD Instinct™ MI300A series
  accelerators, based on the accelerated processing unit (APU) architecture
 , host and device memories are unified into a single physical storage. On 
 an APU, the GPU can access memory in the same way the CPU does, thus avoid
 ing the need for additional data movement (zero-copy). To inform developer
 s of MI300A's expected advantages and potential overheads, we follow an ex
 perimental approach to study our OpenMP implementation that leverages MI30
 0A zero-copy. Performance results show that zero-copy is faster than the l
 egacy “copy” implementation by a ratio of 1.2X-2.3X for a production-ready
  application, but that it incurs up to 11% penalty for one SPECaccel 2023 
 benchmark.\n\nTag: Accelerators, Modeling and Simulation, Performance Eval
 uation and/or Optimization Tools\n\nRegistration Category: Workshop Reg Pa
 ss\n\nSession Chairs: Simon Hammond (National Nuclear Security Administrat
 ion (NNSA)); Sascha Hunold (Technical University of Vienna); and Steven A.
  Wright (University of York, England)\n\n
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