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DTSTART;TZID=America/New_York:20241118T140000
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UID:submissions.supercomputing.org_SC24_sess748_ws_pmbsf108@linklings.com
SUMMARY:Hello SME! Generating Fast Matrix Multiplication Kernels Using the
  Scalable Matrix Extension
DESCRIPTION:Stefan Remke and Alexander Breuer (Friedrich Schiller Universi
 ty Jena, Germany)\n\nModern central processing units (CPUs) feature single
 -instruction, multiple-data pipelines to accelerate compute-intensive floa
 ting-point and fixed-point workloads. Traditionally, these pipelines and c
 orresponding instruction set architectures (ISAs) were designed for vector
  parallelism. The Scalable Matrix Extension (SME) was announced for the Ar
 m architecture in 2021, and Apple's M4 chip is the first to support SME. T
 his paper presents an in-depth study of SME on M4. Our microbenchmarks det
 ermine the maximum floating-point and fixed-point throughput of M4's SME a
 cceleration and study the achievable bandwidth for transfers to and from t
 he matrix registers. Furthermore, we used the insights gained to design a 
 just-in-time code generator for SME-based small matrix multiplications. Th
 e results presented show that M4's SME support is FP32-centric, with an ac
 hievable throughput of over 2.3\,FP32 TFLOPS. Our just-in-time generated s
 mall matrix multiplication kernels outperform the vendor-optimized BLAS im
 plementation in almost all tested configurations.\n\nTag: Accelerators, Mo
 deling and Simulation, Performance Evaluation and/or Optimization Tools\n\
 nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Simon Hammond
  (National Nuclear Security Administration (NNSA)); Sascha Hunold (Technic
 al University of Vienna); and Steven A. Wright (University of York, Englan
 d)\n\n
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