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DTSTART;TZID=America/New_York:20241118T105000
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UID:submissions.supercomputing.org_SC24_sess748_ws_pmbss111@linklings.com
SUMMARY:Microarchitectural Comparison and In-Core Modeling of State-of-the
 -Art CPUs: Grace, Sapphire Rapids, and Genoa
DESCRIPTION:Jan Laukemann (University of Erlangen-Nuremberg, Germany; Erla
 ngen National High Performance Computing Center) and Georg Hager and Gerha
 rd Wellein (Erlangen National High Performance Computing Center)\n\nWith N
 VIDIA’s release of the Grace Superchip, all three big semiconductor compan
 ies in HPC (AMD, Intel, NVIDIA) are currently competing in the race for th
 e best CPU. In this work we analyze the performance of these state-of-the-
 art CPUs and create an accurate in-core performance model for their microa
 rchitectures (Zen 4, Golden Cove, and Neoverse V2), extending the Open Sou
 rce Architecture Code Analyzer (OSACA) tool and comparing it with LLVM-MCA
 . Starting from the peculiarities and upsides/downsides of a single core, 
 we extend our comparison by a variety of microbenchmarks and the capabilit
 ies of a full node. The “write-allocate (WA) evasion” feature, which can a
 utomatically reduce the memory traffic caused by write misses, receives sp
 ecial attention; we show that the Grace Superchip has a next-to-optimal im
 plementation of WA evasion, and that the only way to avoid write allocates
  on Zen 4 is the explicit use of non-temporal stores.\n\nTag: Accelerators
 , Modeling and Simulation, Performance Evaluation and/or Optimization Tool
 s\n\nRegistration Category: Workshop Reg Pass\n\nSession Chairs: Simon Ham
 mond (National Nuclear Security Administration (NNSA)); Sascha Hunold (Tec
 hnical University of Vienna); and Steven A. Wright (University of York, En
 gland)\n\n
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