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UID:submissions.supercomputing.org_SC24_sess758_misc384@linklings.com
SUMMARY:Software-Hardware Codesign Lessons Learned from the IARPA AGILE FO
 RZA Project
DESCRIPTION:Vivek Sarkar (Georgia Institute of Technology)\n\nIn this talk
 , we introduce a new programming system for Partitioned Global Address Spa
 ce (PGAS) applications, where point-to-point remote operations can be expr
 essed as fine-grained asynchronous active messages (or equivalently, as re
 mote asynchronous tasks).  One of the major benefits of this  approach is 
 that it enables asynchronous movement of computation to data as opposed to
  traditional approaches of more synchronous movement of data to computatio
 n.  This approach can be viewed as extending the classical Bulk Synchronou
 s Processing (BSP) model to a Fine-grained-Asynchronous Bulk-Synchronous P
 arallelism (FA-BSP) model. We will discuss an actor-based programming syst
 em to realize the FA-BSP execution model, and present recent results illus
 trating the benefits of this approach on current HPC systems.<br /><br />L
 ooking to the future, we will also discuss ongoing work on hardware suppor
 t of the FA-BSP execution model being undertaken in the Flow-Optimized Rec
 onfigurable Zones of Acceleration (FORZA) project led by Georgia Tech that
  is supported by the IARPA AGILE program.  The FORZA project is pursuing a
  software-hardware co-design approach to address the significant disruptio
 ns currently under way in HPC hardware and software. In hardware, there is
  a Pandora's box of new architectural approaches being proposed to sustain
  performance improvements beyond the end of Moore’s Law.  In software, the
 re is an increased urgency for enabling large-scale data analytics applica
 tions for societal benefits.  To address these challenges, the FORZA proje
 ct is focusing on large-scale graph analytics as an important exemplar of 
 the challenges that need to be addressed by future HPC systems.<br /><br /
 >We would like to acknowledge all participants in the FORZA project from G
 eorgia Tech, Cornelis Networks, Tactical Computing Labs, UC Santa Barbara,
  and U. Notre Dame.  The opinions in this talk are solely those of the spe
 aker and should not be interpreted as necessarily representing the officia
 l policies or endorsements, either expressed or implied, of any of these o
 rganizations, the ODNI, IARPA, or U.S. Government.\n\nTag: Artificial Inte
 lligence/Machine Learning, Codesign\n\nRegistration Category: Workshop Reg
  Pass\n\nSession Chairs: John Feo (Pacific Northwest National Laboratory (
 PNNL)), Jiyuan Zhang (Meta), and Amelie Chi Zhou (Hong Kong Baptist Univer
 sity)\n\n
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