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UID:submissions.supercomputing.org_SC24_sess758_misc389@linklings.com
SUMMARY:European RISC-V based accelerators for HPC - overview and roadmap
DESCRIPTION:Jens Kruger (Fraunhofer Institute for Industrial Mathematics) 
 and Osman Unsal (Barcelona Supercomputing Center (BSC))\n\nThe STX and VEC
  accelerators being developed by the European Processor Initiative (EPI) a
 re targeting the HPC market with different approaches. The STX is co-desig
 ned for algorithms that prevail in hpc simulation applications. It's tuned
  using features from previous architectures like BlueGene, IBM Cell and GP
 Us, and leverages current Open Source developments on hardware and softwar
 e. In order to easily utilize the computational units, it implements novel
  multi-hierarchy offloading features added to OpenMP and automatic DMA ins
 truction injection via LLVM optimization passes. STX is not only a chip - 
 but a full system approach. A company called UNEEC Systems was founded for
  sales and the development of the next generations of STX systems.<br /><b
 r />VEC is a highly efficient vector processor positioned as a general pur
 pose HPC accelerator. Using RISC-V vector extensions and cache coherence, 
 even legacy codes are easily ported to this accelerator through its self-b
 ooting capability. Additionally, VEC is power- and area-efficient through 
 its use of single-ported register file design and simple ring-based inter-
 lane connect while featuring the longest vector length (up to 2048 Double 
 Precision FP elements) of any Vector Processor.<br /><br />This talk will 
 give a brief overview over the concepts behind the two accelerator develop
 ments and presents a roadmap.\n\nTag: Artificial Intelligence/Machine Lear
 ning, Codesign\n\nRegistration Category: Workshop Reg Pass\n\nSession Chai
 rs: John Feo (Pacific Northwest National Laboratory (PNNL)), Jiyuan Zhang 
 (Meta), and Amelie Chi Zhou (Hong Kong Baptist University)\n\n
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