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DTSTART;TZID=America/New_York:20241122T083000
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UID:submissions.supercomputing.org_SC24_sess766@linklings.com
SUMMARY:Tenth International Workshop on Heterogeneous High-performance Rec
 onfigurable Computing (H2RC '24)
DESCRIPTION:As conventional von-Neumann architectures are suffering from r
 ising power densities, we are facing an era with power, energy efficiency,
  and cooling as first-class constraints for scalable HPC. FPGAs can tailor
  the hardware to the application, avoiding overheads and achieving higher 
 hardware efficiency than general-purpose architectures. Leading FPGA manuf
 acturers have made a concerted effort to provide a range of higher-level, 
 easier-to-use high-level programming models for FPGAs, and much of the wor
 k in FPGA-based deep learning is built on these frameworks. Such initiativ
 es are already stimulating new interest within the HPC community around th
 e potential advantages of FPGAs over other architectures. With this in min
 d, this workshop, now in its tenth year, brings together HPC and heterogen
 eous-computing researchers to demonstrate and share experiences on how new
 ly-available high-level programming models, are already empowering HPC sof
 tware developers to directly leverage FPGAs, and to identify future opport
 unities and needs for research in this area.\n\nLowering the Barriers to P
 rogramming FPGAs and AIEs for HPC\n\nWe have seen great advances in the ha
 rdware and software ecosystem for FPGAs in recent years, with the release 
 of ever more powerful FPGAs with specialised hardened components such as A
 I Engines for accelerating compute, and large investment put into tooling,
  high level synthesis and libraries. Howe...\n\n\nNick Brown (Edinburgh Pa
 rallel Computing Centre (EPCC))\n---------------------\nH2RC '24 Opening R
 emarks\n\nKen O'Brien (AMD, Inc.)\n---------------------\nProTEA: Programm
 able Transformer Encoder Acceleration on FPGA\n\nEhsan Kabir (University o
 f Arkansas, Fayetteville); Jason D. Bakos (University of South Carolina); 
 and David Andrews and Miaoqing Huang (University of Arkansas, Fayetteville
 )\n---------------------\nAMD University Program Overview\n\nAndrew Schmid
 t (AMD)\n---------------------\nHPC on a Reconfigurable Substrate with Mac
 hine Learning Support\n\nStatic RAM FPGAs with their reconfigurability yie
 lds options to accomplish instruction set metamorphism or dynamic creation
  of accelerators/coprocessors as needed. In addition, the abundance of mat
 rix multiplications in many HPC problems also gives the possibility to uti
 lize Machine Learning (ML) su...\n\n\nLizy John (The University of Texas a
 t Austin)\n---------------------\nDeLiBA-K: Speeding-up Hardware-Accelerat
 ed Distributed Storage Access by Tighter Linux Kernel Integration and Use 
 of Modern API\n\nWe present DeLiBA-K, an improved version of the Developme
 nt of Linux Block I/O Accelerators (DeLiBA) framework. DeLiBA-K operates a
 t the Linux kernel level, bypassing the user-space interactions of DeLiBA-
 1 and -2 to interact with the block and network I/O kernel stack directly.
  Another critical fea...\n\n\nBabar Khan and Andreas Koch (Technical Unive
 rsity Darmstadt)\n---------------------\nDeveloping a BLAS library for the
  AMD AI Engine\n\nSpatial (dataflow) computer architectures can mitigate t
 he control and performance overhead of classical von Neumann architectures
  such as traditional CPUs.  \n\nDriven by the popularity of Machine Learni
 ng (ML) workload, spatial devices are being marketed as ML inference accel
 erators. Despite providi...\n\n\nTristan Laan and Tiziano De Matteis (Vrij
 e Universiteit Amsterdam)\n---------------------\nH2RC '24 — Morning Break
 \n---------------------\nWhat Should be Used for Reconfigurable HPC, FPGA 
 or Coarser-Grain Reconfigurable Architecture?\n\nKentaro Sano (RIKEN)\n\nT
 ag: Embedded and/or Reconfigurable Systems, Heterogeneous Computing\n\nReg
 istration Category: Workshop Reg Pass\n\nSession Chairs: Jason Bakos (Univ
 ersity of South Carolina); Daniela Campanile (ETH Zürich; Scalable Paralle
 l Computing Laboratory, ETH Zurich); Franck Cappello (Argonne National Lab
 oratory (ANL), University of Illinois); Kenneth O'Brien (Advanced Micro De
 vices (AMD)); Christian Plessl (Paderborn University, Germany); and Meliss
 a C. Smith (Clemson University)
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